1024 lines
43 KiB
C++
1024 lines
43 KiB
C++
/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*-
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* vim: set ts=8 sts=4 et sw=4 tw=99:
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef jit_mips32_MacroAssembler_mips32_h
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#define jit_mips32_MacroAssembler_mips32_h
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#include "jsopcode.h"
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#include "jit/IonCaches.h"
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#include "jit/JitFrames.h"
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#include "jit/mips-shared/MacroAssembler-mips-shared.h"
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#include "jit/MoveResolver.h"
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namespace js {
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namespace jit {
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struct ImmTag : public Imm32
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{
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ImmTag(JSValueTag mask)
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: Imm32(int32_t(mask))
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{ }
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};
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struct ImmType : public ImmTag
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{
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ImmType(JSValueType type)
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: ImmTag(JSVAL_TYPE_TO_TAG(type))
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{ }
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};
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static const ValueOperand JSReturnOperand = ValueOperand(JSReturnReg_Type, JSReturnReg_Data);
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static const ValueOperand softfpReturnOperand = ValueOperand(v1, v0);
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static const int defaultShift = 3;
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static_assert(1 << defaultShift == sizeof(JS::Value), "The defaultShift is wrong");
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static const uint32_t LOW_32_MASK = (1LL << 32) - 1;
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static const int32_t LOW_32_OFFSET = 0;
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static const int32_t HIGH_32_OFFSET = 4;
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class MacroAssemblerMIPS : public MacroAssemblerMIPSShared
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{
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public:
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using MacroAssemblerMIPSShared::ma_b;
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using MacroAssemblerMIPSShared::ma_li;
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using MacroAssemblerMIPSShared::ma_liPatchable;
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using MacroAssemblerMIPSShared::ma_ss;
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using MacroAssemblerMIPSShared::ma_sd;
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using MacroAssemblerMIPSShared::ma_load;
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using MacroAssemblerMIPSShared::ma_store;
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using MacroAssemblerMIPSShared::ma_cmp_set;
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using MacroAssemblerMIPSShared::ma_subTestOverflow;
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void ma_li(Register dest, CodeOffset* label);
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void ma_li(Register dest, ImmWord imm);
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void ma_liPatchable(Register dest, ImmPtr imm);
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void ma_liPatchable(Register dest, ImmWord imm);
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// load
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void ma_load(Register dest, Address address, LoadStoreSize size = SizeWord,
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LoadStoreExtension extension = SignExtend);
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// store
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void ma_store(Register data, Address address, LoadStoreSize size = SizeWord,
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LoadStoreExtension extension = SignExtend);
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// arithmetic based ops
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// add
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template <typename L>
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void ma_addTestOverflow(Register rd, Register rs, Register rt, L overflow);
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template <typename L>
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void ma_addTestOverflow(Register rd, Register rs, Imm32 imm, L overflow);
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// subtract
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void ma_subTestOverflow(Register rd, Register rs, Register rt, Label* overflow);
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// memory
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// shortcut for when we know we're transferring 32 bits of data
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void ma_lw(Register data, Address address);
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void ma_sw(Register data, Address address);
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void ma_sw(Imm32 imm, Address address);
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void ma_sw(Register data, BaseIndex& address);
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void ma_pop(Register r);
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void ma_push(Register r);
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// branches when done from within mips-specific code
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void ma_b(Register lhs, ImmWord imm, Label* l, Condition c, JumpKind jumpKind = MixedJump)
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{
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ma_b(lhs, Imm32(uint32_t(imm.value)), l, c, jumpKind);
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}
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void ma_b(Address addr, ImmWord imm, Label* l, Condition c, JumpKind jumpKind = MixedJump)
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{
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ma_b(addr, Imm32(uint32_t(imm.value)), l, c, jumpKind);
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}
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void ma_b(Register lhs, Address addr, Label* l, Condition c, JumpKind jumpKind = MixedJump);
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void ma_b(Address addr, Imm32 imm, Label* l, Condition c, JumpKind jumpKind = MixedJump);
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void ma_b(Address addr, ImmGCPtr imm, Label* l, Condition c, JumpKind jumpKind = MixedJump);
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void ma_b(Address addr, Register rhs, Label* l, Condition c, JumpKind jumpKind = MixedJump) {
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MOZ_ASSERT(rhs != ScratchRegister);
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ma_lw(ScratchRegister, addr);
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ma_b(ScratchRegister, rhs, l, c, jumpKind);
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}
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// fp instructions
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void ma_lid(FloatRegister dest, double value);
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void ma_mv(FloatRegister src, ValueOperand dest);
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void ma_mv(ValueOperand src, FloatRegister dest);
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void ma_ls(FloatRegister fd, Address address);
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void ma_ld(FloatRegister fd, Address address);
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void ma_sd(FloatRegister fd, Address address);
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void ma_ss(FloatRegister fd, Address address);
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void ma_pop(FloatRegister fs);
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void ma_push(FloatRegister fs);
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void ma_cmp_set(Register dst, Register lhs, ImmPtr imm, Condition c) {
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ma_cmp_set(dst, lhs, Imm32(uint32_t(imm.value)), c);
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}
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void ma_cmp_set(Register dst, Register lhs, Address addr, Condition c) {
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MOZ_ASSERT(lhs != ScratchRegister);
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ma_lw(ScratchRegister, addr);
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ma_cmp_set(dst, lhs, ScratchRegister, c);
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}
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void ma_cmp_set(Register dst, Address lhs, Register rhs, Condition c) {
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MOZ_ASSERT(rhs != ScratchRegister);
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ma_lw(ScratchRegister, lhs);
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ma_cmp_set(dst, ScratchRegister, rhs, c);
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}
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void ma_cmp_set(Register dst, Address lhs, ImmPtr imm, Condition c) {
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ma_lw(SecondScratchReg, lhs);
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ma_cmp_set(dst, SecondScratchReg, imm, c);
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}
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// These fuctions abstract the access to high part of the double precision
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// float register. It is intended to work on both 32 bit and 64 bit
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// floating point coprocessor.
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// :TODO: (Bug 985881) Modify this for N32 ABI to use mthc1 and mfhc1
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void moveToDoubleHi(Register src, FloatRegister dest) {
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as_mtc1(src, getOddPair(dest));
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}
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void moveFromDoubleHi(FloatRegister src, Register dest) {
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as_mfc1(dest, getOddPair(src));
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}
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};
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class MacroAssembler;
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class MacroAssemblerMIPSCompat : public MacroAssemblerMIPS
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{
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public:
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using MacroAssemblerMIPS::call;
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MacroAssemblerMIPSCompat()
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{ }
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void convertBoolToInt32(Register source, Register dest);
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void convertInt32ToDouble(Register src, FloatRegister dest);
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void convertInt32ToDouble(const Address& src, FloatRegister dest);
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void convertInt32ToDouble(const BaseIndex& src, FloatRegister dest);
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void convertUInt32ToDouble(Register src, FloatRegister dest);
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void convertUInt32ToFloat32(Register src, FloatRegister dest);
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void convertDoubleToFloat32(FloatRegister src, FloatRegister dest);
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void convertDoubleToInt32(FloatRegister src, Register dest, Label* fail,
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bool negativeZeroCheck = true);
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void convertFloat32ToInt32(FloatRegister src, Register dest, Label* fail,
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bool negativeZeroCheck = true);
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void convertFloat32ToDouble(FloatRegister src, FloatRegister dest);
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void convertInt32ToFloat32(Register src, FloatRegister dest);
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void convertInt32ToFloat32(const Address& src, FloatRegister dest);
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void computeScaledAddress(const BaseIndex& address, Register dest);
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void computeEffectiveAddress(const Address& address, Register dest) {
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ma_addu(dest, address.base, Imm32(address.offset));
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}
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inline void computeEffectiveAddress(const BaseIndex& address, Register dest);
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void j(Label* dest) {
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ma_b(dest);
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}
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void mov(Register src, Register dest) {
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as_ori(dest, src, 0);
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}
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void mov(ImmWord imm, Register dest) {
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ma_li(dest, imm);
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}
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void mov(ImmPtr imm, Register dest) {
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mov(ImmWord(uintptr_t(imm.value)), dest);
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}
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void mov(Register src, Address dest) {
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MOZ_CRASH("NYI-IC");
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}
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void mov(Address src, Register dest) {
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MOZ_CRASH("NYI-IC");
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}
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void branch(JitCode* c) {
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BufferOffset bo = m_buffer.nextOffset();
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addPendingJump(bo, ImmPtr(c->raw()), Relocation::JITCODE);
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ma_liPatchable(ScratchRegister, ImmPtr(c->raw()));
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as_jr(ScratchRegister);
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as_nop();
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}
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void branch(const Register reg) {
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as_jr(reg);
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as_nop();
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}
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void nop() {
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as_nop();
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}
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void ret() {
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ma_pop(ra);
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as_jr(ra);
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as_nop();
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}
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inline void retn(Imm32 n);
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void push(Imm32 imm) {
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ma_li(ScratchRegister, imm);
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ma_push(ScratchRegister);
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}
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void push(ImmWord imm) {
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ma_li(ScratchRegister, imm);
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ma_push(ScratchRegister);
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}
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void push(ImmGCPtr imm) {
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ma_li(ScratchRegister, imm);
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ma_push(ScratchRegister);
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}
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void push(const Address& address) {
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loadPtr(address, ScratchRegister);
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ma_push(ScratchRegister);
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}
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void push(Register reg) {
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ma_push(reg);
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}
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void push(FloatRegister reg) {
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ma_push(reg);
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}
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void pop(Register reg) {
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ma_pop(reg);
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}
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void pop(FloatRegister reg) {
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ma_pop(reg);
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}
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// Emit a branch that can be toggled to a non-operation. On MIPS we use
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// "andi" instruction to toggle the branch.
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// See ToggleToJmp(), ToggleToCmp().
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CodeOffset toggledJump(Label* label);
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// Emit a "jalr" or "nop" instruction. ToggleCall can be used to patch
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// this instruction.
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CodeOffset toggledCall(JitCode* target, bool enabled);
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static size_t ToggledCallSize(uint8_t* code) {
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// Four instructions used in: MacroAssemblerMIPSCompat::toggledCall
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return 4 * sizeof(uint32_t);
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}
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CodeOffset pushWithPatch(ImmWord imm) {
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CodeOffset label = movWithPatch(imm, ScratchRegister);
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ma_push(ScratchRegister);
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return label;
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}
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CodeOffset movWithPatch(ImmWord imm, Register dest) {
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CodeOffset label = CodeOffset(currentOffset());
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ma_liPatchable(dest, imm);
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return label;
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}
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CodeOffset movWithPatch(ImmPtr imm, Register dest) {
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return movWithPatch(ImmWord(uintptr_t(imm.value)), dest);
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}
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void jump(Label* label) {
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ma_b(label);
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}
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void jump(Register reg) {
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as_jr(reg);
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as_nop();
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}
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void jump(const Address& address) {
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loadPtr(address, ScratchRegister);
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as_jr(ScratchRegister);
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as_nop();
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}
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void jump(JitCode* code) {
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branch(code);
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}
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void jump(wasm::TrapDesc target) {
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ma_b(target);
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}
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void negl(Register reg) {
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ma_negu(reg, reg);
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}
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// Returns the register containing the type tag.
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Register splitTagForTest(const ValueOperand& value) {
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return value.typeReg();
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}
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// unboxing code
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void unboxNonDouble(const ValueOperand& operand, Register dest);
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void unboxNonDouble(const Address& src, Register dest);
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void unboxNonDouble(const BaseIndex& src, Register dest);
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void unboxInt32(const ValueOperand& operand, Register dest);
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void unboxInt32(const Address& src, Register dest);
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void unboxBoolean(const ValueOperand& operand, Register dest);
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void unboxBoolean(const Address& src, Register dest);
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void unboxDouble(const ValueOperand& operand, FloatRegister dest);
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void unboxDouble(const Address& src, FloatRegister dest);
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void unboxString(const ValueOperand& operand, Register dest);
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void unboxString(const Address& src, Register dest);
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void unboxObject(const ValueOperand& src, Register dest);
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void unboxObject(const Address& src, Register dest);
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void unboxObject(const BaseIndex& src, Register dest) { unboxNonDouble(src, dest); }
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void unboxValue(const ValueOperand& src, AnyRegister dest);
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void unboxPrivate(const ValueOperand& src, Register dest);
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void notBoolean(const ValueOperand& val) {
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as_xori(val.payloadReg(), val.payloadReg(), 1);
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}
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// boxing code
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void boxDouble(FloatRegister src, const ValueOperand& dest);
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void boxNonDouble(JSValueType type, Register src, const ValueOperand& dest);
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// Extended unboxing API. If the payload is already in a register, returns
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// that register. Otherwise, provides a move to the given scratch register,
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// and returns that.
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Register extractObject(const Address& address, Register scratch);
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Register extractObject(const ValueOperand& value, Register scratch) {
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return value.payloadReg();
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}
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Register extractInt32(const ValueOperand& value, Register scratch) {
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return value.payloadReg();
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}
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Register extractBoolean(const ValueOperand& value, Register scratch) {
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return value.payloadReg();
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}
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Register extractTag(const Address& address, Register scratch);
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Register extractTag(const BaseIndex& address, Register scratch);
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Register extractTag(const ValueOperand& value, Register scratch) {
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return value.typeReg();
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}
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void boolValueToDouble(const ValueOperand& operand, FloatRegister dest);
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void int32ValueToDouble(const ValueOperand& operand, FloatRegister dest);
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void loadInt32OrDouble(const Address& address, FloatRegister dest);
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void loadInt32OrDouble(Register base, Register index,
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FloatRegister dest, int32_t shift = defaultShift);
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void loadConstantDouble(double dp, FloatRegister dest);
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void loadConstantDouble(wasm::RawF64 d, FloatRegister dest);
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void boolValueToFloat32(const ValueOperand& operand, FloatRegister dest);
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void int32ValueToFloat32(const ValueOperand& operand, FloatRegister dest);
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void loadConstantFloat32(float f, FloatRegister dest);
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void loadConstantFloat32(wasm::RawF32 f, FloatRegister dest);
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void testNullSet(Condition cond, const ValueOperand& value, Register dest);
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void testObjectSet(Condition cond, const ValueOperand& value, Register dest);
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void testUndefinedSet(Condition cond, const ValueOperand& value, Register dest);
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// higher level tag testing code
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Operand ToPayload(Operand base);
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Address ToPayload(Address base) {
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return ToPayload(Operand(base)).toAddress();
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}
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protected:
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Operand ToType(Operand base);
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Address ToType(Address base) {
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return ToType(Operand(base)).toAddress();
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}
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uint32_t getType(const Value& val);
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void moveData(const Value& val, Register data);
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public:
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void moveValue(const Value& val, Register type, Register data);
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CodeOffsetJump backedgeJump(RepatchLabel* label, Label* documentation = nullptr);
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CodeOffsetJump jumpWithPatch(RepatchLabel* label, Label* documentation = nullptr);
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void loadUnboxedValue(Address address, MIRType type, AnyRegister dest) {
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if (dest.isFloat())
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loadInt32OrDouble(address, dest.fpu());
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else
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ma_lw(dest.gpr(), address);
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}
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void loadUnboxedValue(BaseIndex address, MIRType type, AnyRegister dest) {
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if (dest.isFloat())
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loadInt32OrDouble(address.base, address.index, dest.fpu(), address.scale);
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else
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load32(address, dest.gpr());
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}
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template <typename T>
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void storeUnboxedValue(ConstantOrRegister value, MIRType valueType, const T& dest,
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MIRType slotType);
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template <typename T>
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void storeUnboxedPayload(ValueOperand value, T address, size_t nbytes) {
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switch (nbytes) {
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case 4:
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store32(value.payloadReg(), address);
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return;
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case 1:
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store8(value.payloadReg(), address);
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return;
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default: MOZ_CRASH("Bad payload width");
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}
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}
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void moveValue(const Value& val, const ValueOperand& dest);
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void moveValue(const ValueOperand& src, const ValueOperand& dest) {
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Register s0 = src.typeReg(), d0 = dest.typeReg(),
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s1 = src.payloadReg(), d1 = dest.payloadReg();
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// Either one or both of the source registers could be the same as a
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// destination register.
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if (s1 == d0) {
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if (s0 == d1) {
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// If both are, this is just a swap of two registers.
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MOZ_ASSERT(d1 != ScratchRegister);
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MOZ_ASSERT(d0 != ScratchRegister);
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move32(d1, ScratchRegister);
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move32(d0, d1);
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move32(ScratchRegister, d0);
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return;
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}
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// If only one is, copy that source first.
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mozilla::Swap(s0, s1);
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mozilla::Swap(d0, d1);
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}
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if (s0 != d0)
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move32(s0, d0);
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if (s1 != d1)
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move32(s1, d1);
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}
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void storeValue(ValueOperand val, Operand dst);
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void storeValue(ValueOperand val, const BaseIndex& dest);
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void storeValue(JSValueType type, Register reg, BaseIndex dest);
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void storeValue(ValueOperand val, const Address& dest);
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void storeValue(JSValueType type, Register reg, Address dest);
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void storeValue(const Value& val, Address dest);
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void storeValue(const Value& val, BaseIndex dest);
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void storeValue(const Address& src, const Address& dest, Register temp) {
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load32(ToType(src), temp);
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store32(temp, ToType(dest));
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load32(ToPayload(src), temp);
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store32(temp, ToPayload(dest));
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}
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void loadValue(Address src, ValueOperand val);
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void loadValue(Operand dest, ValueOperand val) {
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loadValue(dest.toAddress(), val);
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}
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void loadValue(const BaseIndex& addr, ValueOperand val);
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void tagValue(JSValueType type, Register payload, ValueOperand dest);
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void pushValue(ValueOperand val);
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void popValue(ValueOperand val);
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void pushValue(const Value& val) {
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push(Imm32(val.toNunboxTag()));
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if (val.isGCThing())
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push(ImmGCPtr(val.toGCThing()));
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else
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push(Imm32(val.toNunboxPayload()));
|
|
}
|
|
void pushValue(JSValueType type, Register reg) {
|
|
push(ImmTag(JSVAL_TYPE_TO_TAG(type)));
|
|
ma_push(reg);
|
|
}
|
|
void pushValue(const Address& addr);
|
|
|
|
void storePayload(const Value& val, Address dest);
|
|
void storePayload(Register src, Address dest);
|
|
void storePayload(const Value& val, const BaseIndex& dest);
|
|
void storePayload(Register src, const BaseIndex& dest);
|
|
void storeTypeTag(ImmTag tag, Address dest);
|
|
void storeTypeTag(ImmTag tag, const BaseIndex& dest);
|
|
|
|
void handleFailureWithHandlerTail(void* handler);
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// Common interface.
|
|
/////////////////////////////////////////////////////////////////
|
|
public:
|
|
// The following functions are exposed for use in platform-shared code.
|
|
|
|
template<typename T>
|
|
void compareExchange8SignExtend(const T& mem, Register oldval, Register newval, Register valueTemp,
|
|
Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
compareExchange(1, true, mem, oldval, newval, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T>
|
|
void compareExchange8ZeroExtend(const T& mem, Register oldval, Register newval, Register valueTemp,
|
|
Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
compareExchange(1, false, mem, oldval, newval, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T>
|
|
void compareExchange16SignExtend(const T& mem, Register oldval, Register newval, Register valueTemp,
|
|
Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
compareExchange(2, true, mem, oldval, newval, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T>
|
|
void compareExchange16ZeroExtend(const T& mem, Register oldval, Register newval, Register valueTemp,
|
|
Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
compareExchange(2, false, mem, oldval, newval, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T>
|
|
void compareExchange32(const T& mem, Register oldval, Register newval, Register valueTemp,
|
|
Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
compareExchange(4, false, mem, oldval, newval, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
|
|
template<typename T>
|
|
void atomicExchange8SignExtend(const T& mem, Register value, Register valueTemp,
|
|
Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicExchange(1, true, mem, value, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T>
|
|
void atomicExchange8ZeroExtend(const T& mem, Register value, Register valueTemp,
|
|
Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicExchange(1, false, mem, value, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T>
|
|
void atomicExchange16SignExtend(const T& mem, Register value, Register valueTemp,
|
|
Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicExchange(2, true, mem, value, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T>
|
|
void atomicExchange16ZeroExtend(const T& mem, Register value, Register valueTemp,
|
|
Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicExchange(2, false, mem, value, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T>
|
|
void atomicExchange32(const T& mem, Register value, Register valueTemp,
|
|
Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicExchange(4, false, mem, value, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
|
|
template<typename T, typename S>
|
|
void atomicFetchAdd8SignExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(1, true, AtomicFetchAddOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchAdd8ZeroExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(1, false, AtomicFetchAddOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchAdd16SignExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(2, true, AtomicFetchAddOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchAdd16ZeroExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(2, false, AtomicFetchAddOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchAdd32(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(4, false, AtomicFetchAddOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicAdd8(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(1, AtomicFetchAddOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicAdd16(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(2, AtomicFetchAddOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicAdd32(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(4, AtomicFetchAddOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
|
|
template<typename T, typename S>
|
|
void atomicFetchSub8SignExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(1, true, AtomicFetchSubOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchSub8ZeroExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(1, false, AtomicFetchSubOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchSub16SignExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(2, true, AtomicFetchSubOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchSub16ZeroExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(2, false, AtomicFetchSubOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchSub32(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(4, false, AtomicFetchSubOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicSub8(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(1, AtomicFetchSubOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicSub16(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(2, AtomicFetchSubOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicSub32(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(4, AtomicFetchSubOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
|
|
template<typename T, typename S>
|
|
void atomicFetchAnd8SignExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(1, true, AtomicFetchAndOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchAnd8ZeroExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(1, false, AtomicFetchAndOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchAnd16SignExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(2, true, AtomicFetchAndOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchAnd16ZeroExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(2, false, AtomicFetchAndOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchAnd32(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(4, false, AtomicFetchAndOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicAnd8(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(1, AtomicFetchAndOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicAnd16(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(2, AtomicFetchAndOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicAnd32(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(4, AtomicFetchAndOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
|
|
template<typename T, typename S>
|
|
void atomicFetchOr8SignExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(1, true, AtomicFetchOrOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchOr8ZeroExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(1, false, AtomicFetchOrOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchOr16SignExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(2, true, AtomicFetchOrOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchOr16ZeroExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(2, false, AtomicFetchOrOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchOr32(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(4, false, AtomicFetchOrOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicOr8(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(1, AtomicFetchOrOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicOr16(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(2, AtomicFetchOrOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicOr32(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(4, AtomicFetchOrOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
|
|
template<typename T, typename S>
|
|
void atomicFetchXor8SignExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(1, true, AtomicFetchXorOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchXor8ZeroExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(1, false, AtomicFetchXorOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchXor16SignExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(2, true, AtomicFetchXorOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchXor16ZeroExtend(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(2, false, AtomicFetchXorOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template<typename T, typename S>
|
|
void atomicFetchXor32(const S& value, const T& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp, Register output)
|
|
{
|
|
atomicFetchOp(4, false, AtomicFetchXorOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp, output);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicXor8(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(1, AtomicFetchXorOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicXor16(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(2, AtomicFetchXorOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
template <typename T, typename S>
|
|
void atomicXor32(const T& value, const S& mem, Register flagTemp,
|
|
Register valueTemp, Register offsetTemp, Register maskTemp)
|
|
{
|
|
atomicEffectOp(4, AtomicFetchXorOp, value, mem, flagTemp, valueTemp, offsetTemp, maskTemp);
|
|
}
|
|
|
|
template<typename T>
|
|
void compareExchangeToTypedIntArray(Scalar::Type arrayType, const T& mem, Register oldval, Register newval,
|
|
Register temp, Register valueTemp, Register offsetTemp, Register maskTemp,
|
|
AnyRegister output);
|
|
|
|
template<typename T>
|
|
void atomicExchangeToTypedIntArray(Scalar::Type arrayType, const T& mem, Register value,
|
|
Register temp, Register valueTemp, Register offsetTemp, Register maskTemp,
|
|
AnyRegister output);
|
|
|
|
inline void incrementInt32Value(const Address& addr);
|
|
|
|
void move32(Imm32 imm, Register dest);
|
|
void move32(Register src, Register dest);
|
|
|
|
void movePtr(Register src, Register dest);
|
|
void movePtr(ImmWord imm, Register dest);
|
|
void movePtr(ImmPtr imm, Register dest);
|
|
void movePtr(wasm::SymbolicAddress imm, Register dest);
|
|
void movePtr(ImmGCPtr imm, Register dest);
|
|
|
|
void load8SignExtend(const Address& address, Register dest);
|
|
void load8SignExtend(const BaseIndex& src, Register dest);
|
|
|
|
void load8ZeroExtend(const Address& address, Register dest);
|
|
void load8ZeroExtend(const BaseIndex& src, Register dest);
|
|
|
|
void load16SignExtend(const Address& address, Register dest);
|
|
void load16SignExtend(const BaseIndex& src, Register dest);
|
|
|
|
void load16ZeroExtend(const Address& address, Register dest);
|
|
void load16ZeroExtend(const BaseIndex& src, Register dest);
|
|
|
|
void load32(const Address& address, Register dest);
|
|
void load32(const BaseIndex& address, Register dest);
|
|
void load32(AbsoluteAddress address, Register dest);
|
|
void load32(wasm::SymbolicAddress address, Register dest);
|
|
void load64(const Address& address, Register64 dest) {
|
|
load32(Address(address.base, address.offset + INT64LOW_OFFSET), dest.low);
|
|
int32_t highOffset = (address.offset < 0) ? -int32_t(INT64HIGH_OFFSET) : INT64HIGH_OFFSET;
|
|
load32(Address(address.base, address.offset + highOffset), dest.high);
|
|
}
|
|
|
|
void loadPtr(const Address& address, Register dest);
|
|
void loadPtr(const BaseIndex& src, Register dest);
|
|
void loadPtr(AbsoluteAddress address, Register dest);
|
|
void loadPtr(wasm::SymbolicAddress address, Register dest);
|
|
|
|
void loadPrivate(const Address& address, Register dest);
|
|
|
|
void loadInt32x1(const Address& addr, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void loadInt32x1(const BaseIndex& addr, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void loadInt32x2(const Address& addr, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void loadInt32x2(const BaseIndex& addr, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void loadInt32x3(const Address& src, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void loadInt32x3(const BaseIndex& src, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void storeInt32x1(FloatRegister src, const Address& dest) { MOZ_CRASH("NYI"); }
|
|
void storeInt32x1(FloatRegister src, const BaseIndex& dest) { MOZ_CRASH("NYI"); }
|
|
void storeInt32x2(FloatRegister src, const Address& dest) { MOZ_CRASH("NYI"); }
|
|
void storeInt32x2(FloatRegister src, const BaseIndex& dest) { MOZ_CRASH("NYI"); }
|
|
void storeInt32x3(FloatRegister src, const Address& dest) { MOZ_CRASH("NYI"); }
|
|
void storeInt32x3(FloatRegister src, const BaseIndex& dest) { MOZ_CRASH("NYI"); }
|
|
void loadAlignedSimd128Int(const Address& addr, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void storeAlignedSimd128Int(FloatRegister src, Address addr) { MOZ_CRASH("NYI"); }
|
|
void loadUnalignedSimd128Int(const Address& addr, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void loadUnalignedSimd128Int(const BaseIndex& addr, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void storeUnalignedSimd128Int(FloatRegister src, Address addr) { MOZ_CRASH("NYI"); }
|
|
void storeUnalignedSimd128Int(FloatRegister src, BaseIndex addr) { MOZ_CRASH("NYI"); }
|
|
|
|
void loadFloat32x3(const Address& src, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void loadFloat32x3(const BaseIndex& src, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void loadAlignedSimd128Float(const Address& addr, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void storeAlignedSimd128Float(FloatRegister src, Address addr) { MOZ_CRASH("NYI"); }
|
|
void loadUnalignedSimd128Float(const Address& addr, FloatRegister dest) { MOZ_CRASH("NYI"); }
|
|
void loadUnalignedSimd128Float(const BaseIndex& addr, FloatRegister dest) { MOZ_CRASH("NYI"); }
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void storeUnalignedSimd128Float(FloatRegister src, Address addr) { MOZ_CRASH("NYI"); }
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void storeUnalignedSimd128Float(FloatRegister src, BaseIndex addr) { MOZ_CRASH("NYI"); }
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void loadDouble(const Address& addr, FloatRegister dest);
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void loadDouble(const BaseIndex& src, FloatRegister dest);
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void loadUnalignedDouble(const wasm::MemoryAccessDesc& access, const BaseIndex& src,
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Register temp, FloatRegister dest);
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// Load a float value into a register, then expand it to a double.
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void loadFloatAsDouble(const Address& addr, FloatRegister dest);
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void loadFloatAsDouble(const BaseIndex& src, FloatRegister dest);
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void loadFloat32(const Address& addr, FloatRegister dest);
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void loadFloat32(const BaseIndex& src, FloatRegister dest);
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void loadUnalignedFloat32(const wasm::MemoryAccessDesc& access, const BaseIndex& src,
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Register temp, FloatRegister dest);
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void store8(Register src, const Address& address);
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void store8(Imm32 imm, const Address& address);
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void store8(Register src, const BaseIndex& address);
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void store8(Imm32 imm, const BaseIndex& address);
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|
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void store16(Register src, const Address& address);
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void store16(Imm32 imm, const Address& address);
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void store16(Register src, const BaseIndex& address);
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void store16(Imm32 imm, const BaseIndex& address);
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|
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void store32(Register src, AbsoluteAddress address);
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void store32(Register src, const Address& address);
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void store32(Register src, const BaseIndex& address);
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void store32(Imm32 src, const Address& address);
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void store32(Imm32 src, const BaseIndex& address);
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|
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// NOTE: This will use second scratch on MIPS. Only ARM needs the
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|
// implementation without second scratch.
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void store32_NoSecondScratch(Imm32 src, const Address& address) {
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store32(src, address);
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}
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|
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void store64(Register64 src, Address address) {
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store32(src.low, Address(address.base, address.offset + LOW_32_OFFSET));
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store32(src.high, Address(address.base, address.offset + HIGH_32_OFFSET));
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}
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|
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void store64(Imm64 imm, Address address) {
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store32(imm.low(), Address(address.base, address.offset + LOW_32_OFFSET));
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store32(imm.hi(), Address(address.base, address.offset + HIGH_32_OFFSET));
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}
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template <typename T> void storePtr(ImmWord imm, T address);
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template <typename T> void storePtr(ImmPtr imm, T address);
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template <typename T> void storePtr(ImmGCPtr imm, T address);
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|
void storePtr(Register src, const Address& address);
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|
void storePtr(Register src, const BaseIndex& address);
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|
void storePtr(Register src, AbsoluteAddress dest);
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|
|
|
void storeUnalignedFloat32(const wasm::MemoryAccessDesc& access, FloatRegister src,
|
|
Register temp, const BaseIndex& dest);
|
|
void storeUnalignedDouble(const wasm::MemoryAccessDesc& access, FloatRegister src,
|
|
Register temp, const BaseIndex& dest);
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|
|
|
void moveDouble(FloatRegister src, FloatRegister dest) {
|
|
as_movd(dest, src);
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|
}
|
|
|
|
void zeroDouble(FloatRegister reg) {
|
|
moveToDoubleLo(zero, reg);
|
|
moveToDoubleHi(zero, reg);
|
|
}
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|
|
|
static bool convertUInt64ToDoubleNeedsTemp();
|
|
void convertUInt64ToDouble(Register64 src, FloatRegister dest, Register temp);
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|
|
|
void breakpoint();
|
|
|
|
void checkStackAlignment();
|
|
|
|
void alignStackPointer();
|
|
void restoreStackPointer();
|
|
static void calculateAlignedStackPointer(void** stackPointer);
|
|
|
|
// If source is a double, load it into dest. If source is int32,
|
|
// convert it to double. Else, branch to failure.
|
|
void ensureDouble(const ValueOperand& source, FloatRegister dest, Label* failure);
|
|
|
|
protected:
|
|
bool buildOOLFakeExitFrame(void* fakeReturnAddr);
|
|
|
|
public:
|
|
CodeOffset labelForPatch() {
|
|
return CodeOffset(nextOffset().getOffset());
|
|
}
|
|
|
|
void lea(Operand addr, Register dest) {
|
|
ma_addu(dest, addr.baseReg(), Imm32(addr.disp()));
|
|
}
|
|
|
|
void abiret() {
|
|
as_jr(ra);
|
|
as_nop();
|
|
}
|
|
|
|
void ma_storeImm(Imm32 imm, const Address& addr) {
|
|
ma_sw(imm, addr);
|
|
}
|
|
|
|
void moveFloat32(FloatRegister src, FloatRegister dest) {
|
|
as_movs(dest, src);
|
|
}
|
|
void loadWasmGlobalPtr(uint32_t globalDataOffset, Register dest) {
|
|
loadPtr(Address(GlobalReg, globalDataOffset - WasmGlobalRegBias), dest);
|
|
}
|
|
void loadWasmPinnedRegsFromTls() {
|
|
loadPtr(Address(WasmTlsReg, offsetof(wasm::TlsData, memoryBase)), HeapReg);
|
|
loadPtr(Address(WasmTlsReg, offsetof(wasm::TlsData, globalData)), GlobalReg);
|
|
ma_addu(GlobalReg, Imm32(WasmGlobalRegBias));
|
|
}
|
|
|
|
// Instrumentation for entering and leaving the profiler.
|
|
void profilerEnterFrame(Register framePtr, Register scratch);
|
|
void profilerExitFrame();
|
|
};
|
|
|
|
typedef MacroAssemblerMIPSCompat MacroAssemblerSpecific;
|
|
|
|
} // namespace jit
|
|
} // namespace js
|
|
|
|
#endif /* jit_mips32_MacroAssembler_mips32_h */
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